A methodolgy for characterizing cell testability

نویسندگان

  • Alvin Jee
  • F. Joel Ferguson
چکیده

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Designing Testable Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Dissertation Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Chapter 2: Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Gate and Circuit Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.2 Cell Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Conclusion and Problem Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 3: Defining Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.1 Quality Level and Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2 Influences on Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.3 Measuring Effective Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Chapter 4: Potential Benefit of Physical Design for Testability . . . . . . . . . . . . . . . . . . . 24 4.1 Experiment Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Distribution of Bridge Fault WCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 WCA Coverage of Stuck-At Test Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.1 Characterizing the Behavior of Shorts . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.2 Fault Simulating the Realistic Shorts . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4 Not Detected Versus Not Detectable Shorts within Cells . . . . . . . . . . . . . . . . . 30 4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chapter 5: Characterizing A Cell’s Effective Testability . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 Designing Cells with High Effective Testability . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 Characterizing the Test Environment and Circuit Topology . . . . . . . . . 34 5.1.2 Assessing A Cell’s Effective Testability . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 An Implementation of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.1 Test Environment and Circuit Topology Characterization . . . . . . . . . . . 39 5.2.2 Assessing A Cell’s Effective Testability . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Chapter 6: Application of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1 Cell Input Pattern Profiles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 Cell Effective Testability Assessments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.1 Improving the Complete Effective Testability of a Cell . . . . . . . . . . . . . 47 6.2.2 Improving the Partial Effective Testability of a Cell . . . . . . . . . . . . . . . 51 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chapter 7: Summary and Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Chapter 8: Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Appendix A: Fabrication Defect Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Chapter 9: Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...

متن کامل

Designing of Testable Reversible QCA Circuits Using a New Reversible MUX 2×1

Recently testing of Quantum-dot Cellular Automata (QCA) Circuits has attracted a lot of attention. In this paper, QCA is investigated for testable implementations of reversible logic. To amplify testability in Reversible QCA circuits, a test method regarding to Built In Self Test technique is developed for detecting all simulated defects. A new Reversible QCA MUX 2×1 desig...

متن کامل

Testability Analysis of the Communication Protocols Modeled by Relations1

The cost of the test activity constitutes an important part of the total development cost. To make test easier (cost, time, and efforts), the consideration of test problems before the implementation phase is now necessary. This early consideration is known as Design for testability (DFT). The design of testable software does not consist solely in applying methods that improve the testability bu...

متن کامل

Pii: S0950-5849(99)00033-6

To deal with the increased complexity related to the testing of communications software, we propose the integration and application of finite state machine based specification transformations and testability measures early in the communications software development process. Based on this integration, the testability of a given design is estimated and appropriate specification transformations ar...

متن کامل

Testability-driven High-level Synthesis

This paper describes a new approach to integrate testability consideration into high-level synthesis. The approach is based on an iterative technique for high-level synthesis which utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. A testability analysis algorithm is used to analyze the intermediate result...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1997